399 Design of an 8-Channel 40 GS/s 20 mW/Ch Waveform Sampling ASIC in 65 nm CMOS

Original Uploaded File: Download PisaMeeting_NIMA_PSEC5_revisions_v2.pdf

Description: Paper derived from Jinseo Park's talk at the Pisa 2024 meeting

Ahan Datta
Camden Ertley
Henry J Frisch
Mary Heintz
Eric Oberla
joe Pastika
Hector D. Rico-Aniles
Paul Rubinov
Richmond Yeung
Andrew Arzac
Jinseo Park
Evan Angelico
Davide Braga
Troy England
Xiaoran Wang
Farah Fahim

Electronics

Conference Proceedings
Papers in preparation (posted on arXiv)
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