398 CPAD 2024 Abstracts

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Description: Design of an 8-Channel 40 GS/s 20 mW/Ch Waveform Sampling ASIC in 65 nm CMOS Digital Design and Implementation for the PSEC5 40 GS/s waveform-sampling ASIC A Modular Test System for the PSEC5 40 GS/s waveform-sampling ASIC The Role of Young University Undergraduates Guided by National Lab Experts, in the Design of PSEC5, a 40 GS/sec 4GHz 8-Channel Mixed-Signal ASIC

Andrew Aarzac
Evan Angelico
Ahan Datta
Henry J Frisch
Mary Heintz
Eric Oberla
Jinseo Park
joe Pastika
Hector D. Rico-Aniles
Paul Rubinov
Richmond Yeung

Electronics

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